1. Field of the Invention
The present invention is directed to an apparatus and a method for synchronization of an asynchronous signal in synthesis and simulation of a clocked circuit and, in particular, to an apparatus and a method with which a critical condition can be separated from an uncritical condition in the time behavior of a signal in a clocked circuit in the implementation of a simulation.
2. Description of the Related Art
Application-specific integrated circuits (ASICs), customer-specific integrated circuits (full-custom ICs) as well as their mixed forms (semi-custom ICs) are being increasingly tested for logical function and time behavior in prior to manufacture by stimulation.
A circuit is usually described for stimulation in a hardware description language such as, a VHDL code, and the logical function of the circuit is tested with a VHDL logic simulator. A test of the time behavior of the signals, however, cannot be implemented with such a logic simulator on the basis of the hardware description language (VHDL code).
For implementing a test of the time behavior of a circuit, the hardware description language (VHDL code) must be converted by a synthesis tool into a network list that represents a further code (circuit plan) of the original circuit. On the basis of this network list, the time behavior of the signals in the circuit can also be acquired or, tested with a logic/timing simulator.
Given such a test of the time behavior of the signals in the circuit or, respectively, timing simulation, time-critical signal statusses in the circuit can have been recognized and eliminated in the simulation. Such a signal status may be explained by way of example on the basis of a clocked flip-flop, but the invention is not limited to such component parts.
FIG. 1 shows a circuit diagram of a traditional flip-flop FF1 with an input terminal D, a clock input CLK and an output terminal Q. FIG. 2 shows an exemplary signal-time behavior with which no time-critical signal status occurs in the clocked flip-flop FF1. Characteristics typical of the component derive dependent on the technology employed or, respectively, on the technical realization of an electronic component (for example, a flip-flop) in a semiconductor. The characteristics critical for the flip-flop FF1 according to FIG. 1 are the setup time ts and the hold time th. These times define a time span for the flip-flop FF1 shown in FIG. 1 before and after the leading edge of the clock signal CLK at which a dependable acceptance of a signal pending at the input D ensues. Since, according to FIG. 2, the signal at the input D already has a stable value “1” before the time span ts and th, the signal at the output Q of the flip-flop FF1 is dependably set to “1” at the time of the leading edge of the clock signal CLK.
In comparison, FIG. 3 shows a signal-time behavior with which a violation of the setup time ts occurs, for which reason the output Q assumes an undefined condition. According to FIG. 3, the leading edge of the signal at the input of the flip-flop FF1 falls into the time span ts of the setup time, for which reason the signal at the output Q initially proceeds into a metastable condition I in order to then assume an undefined but fixed condition II (“0” or “1”) after the time tm. The metastable condition has an approximate time durationtm=5×tPD, where tPD is the running time in the flip-flop FF1 from the clock input CLK to the output Q. The time duration for tm for the metastable condition I is dependent on the technology employed and on the semiconductor employed. After the metastable condition I, in which the output signal Q usually oscillates, the output signal Q enters into a stable but undefined condition II that is arbitrarily and randomly assumed. The same is true for a violation of the hold time.
Such unknown, i.e., metastable or, undefined conditions in the signal-time behavior are undesired since they disadvantageously influence the following circuit elements that interpret this signal and are generally referred to below as setup/hold time violations.
Particularly in the implementation of a logic/timing simulation test of the signal-time behavior of a clock circuit, the above-described setup/hold time violation has such an effect that the simulator outputs an “unknown” status for the affected signal, signals or circuit elements that are dependent on this affected signal circuit-oriented terms can no longer be tested. This leads to considerable problems in a majority of applications (e.g., an abort of the simulation).
FIG. 4 shows a clock circuit that is composed of a first ASIC module A1 and of a second ASIC module A2. The ASIC module A1 is operated with a first clock signal CLKI, for example 16 MHz, and the ASIC module A2 is operated with a second clock signal CLKII, for example 25 MHz. The clocks CLKI and CLKII are not synchronized, resulting in the problem that the ASIC module A1 outputs an output signal S_ASYNC that is asynchronous relative to the clock signal CLKII. The signal S_ASYNC is asynchronous relative to the input clock signal CLKII. Setup/hold time violations will occur in an input circuit of the ASIC module A2. For a logic/timing simulation of the circuit to be implemented according to FIG. 4, the entire ASIC module A2 thus can not be tested in view of its time behavior since there is the potential risk of setup/hold time violations at the input FF of ASIC module A2. In order to avoid such an outcome, the test of a setup/hold time violation can be generally disabled or the signal curve of the respective signals is intentionally modified for the implementation of the simulation; for example, the signal S_ASYNC is generated synchronous with the clock CLKII. A further possibility is to perform a manual intervention into the network list of the circuit to be simulated in order to selectively deactivate the test or, the setup time violation from the input circuit (flip-flop).
All of these measures, however, are time-consuming, susceptible to error, or deteriorate the simulation result since the simulation is not based on the real time behavior of the signals.